GALS Methodology for Substrate Noise Reduction in BiCMOS Technologies

The coupling of simultaneous switching noise through the substrate presents an important issue to integration of both noisy digital and sensitive analog circuitry in mixedsignal integrated circuits. Noise is generated by digital aggressor circuits, it further propagates through the common substrate, and finally impacts the performance of analog victim circuitry through body effect and capacitive coupling. In order to make the analog circuitry, and thus the entire system, more reliable and less prone to errors caused by substrate noise coupling, this noise has to be estimated and suppressed. The goal of this work is to explore the possibility of actively reducing substrate noise by applying GALS (globallyasynchronous, locally synchronous) architectures in digital design. GALS systems consist of locally synchronous modules (LSM), which communicate asynchronously between each other. [1] Each of the LSMs has its own clock. It has already been shown that, thanks to the fact that LSM clocks are naturally desynchronized, applying GALS techniques can reduce spectral peaks of switching current [2], as well as timedomain peaks of voltage oscillations on supply and ground lines. [3] As those oscillations are important source of substrate noise, GALS is a good candidate for reducing the substrate noise too. However, an analysis of substrate noise reduction with GALS technique has never been made before, and it’s the main task of this PhD work. In order to analyze the impact of GALS architectures to substrate noise, an appropriate model of substrate noise coupling has to be developed. The model should be applicable for use in an early phase of design, before exact details of layout are known. It should be simple enough to provide analysis at system level, and it should aim at full-chip analysis. This work focuses on noise coupling through lightly doped substrates, because that kind of substrate is predominantly used in technologies for mixed-signal ICs, including BiCMOS technologies. Such substrates are mostly uniformly doped, and due to light doping they have high resistivity. Thus it’s impossible to approximately model a lightly doped substrate as a single node, and it has to be modeled in form of an impedance mesh. [4] The initial impedance mesh can be obtained by discretizing the substrate and writing the Poisson’s equation for each of the discretization domains. [5] Mesh impedances consist of resistive and capacitive component connected in parallel. At lower frequencies, the capacitive component can be neglected, and the substrate can be approximated as purely resistive. [5] For most of the packages, direct power coupling through substrate contacts is the dominant noise source for lightly doped substrates. [4][6] Thus, other noise sources can be neglected, and the only ports remaining within aggressors are actually substrate contacts. [7] If the package parasitics are dominant compared to on-chip parasitics, an equal ground bounce approximation can be applied, which means that ground bounce voltage can be considered the same within a single power domain. [7] As a consequence, all the substrate contacts in a digital aggressor, which share the same biasing, can be shorted in the model. In [8], we proposed a coarse model for lightly-doped substrates. A variable discretization step has been applied, equal to minimum substrate contact size on the surface, and getting coarser for layers further away from the surface. Contact impedances were neglected, as they’re much smaller than the substrate impedances between the contacts. All the noise sources other than direct coupling through substrate contacts have been neglected. An equal ground bounce approximation has been applied, and that way each digital aggressor has been reduced to a single node and a single noise source. However, the reduction procedure is dependent on the initial position of contacts, i.e. on the layout. In order to obtain the simplified model before the exact layout data are known, some assumptions about layout have to be made. In digital circuits, all the standard cells have the same height, and they’re oriented so that two adjacent rows share the same supply or ground stripe. Because of that, we assumed a regular distribution of contacts, as presented on the Fig. 1. [8] This approximation has been analyzed by performing the extraction with modified contact distributions, and it has been shown that only a small additional error, with an order of magnitude of 1%, is introduced by this assumption. [8] Further improvements of this model will include improved discretization strategy, in order to enable analysis of dies with larger area. The idea is to make the discretization step on the surface coarser, and to scale the obtained impedances accordingly, in order to properly account for the contact size and density. To obtain a full substrate noise coupling model, ground bounce as a dominant noise source at aggressor side also has to be modelled. In [2], the switching current, which causes the ground bounce, has been modeled in frequency domain for both GALS and synchronous systems. The time domain current 2015 MEDIAN Finale Workshop